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december 2007 rev 6 1/32 1 l6258ex pwm controlled high current dmos universal motor driver features able to drive both windings of a bipolar stepper motor or two dc motors output current up to 1.5a each winding wide voltage range: 12v to 40v four quadrant current control, ideal for microstepping and dc motor control precision pwm control no need for recirculation diodes ttl/cmos compatible inputs cross conduction protection thermal shutdow description l6258ex is a dual full bridge for motor control applications realized in bcd technology, with the capability of driving both windings of a bipolar stepper motor or bidirectionally control two dc motors. l6258ex and a few external components form a complete control and drive circuit. it has high efficiency phase shift chopping that allows a very low current ripple at the lowest current control levels, and makes this device ideal for steppers as well as for dc motors. the power stage is a dual dmos full bridge capable of sustaining up to 40v, and includes the diodes for current recirculation.the output current capability is 1.5a per winding in continuous mode, with peak start-up current up to 2a. a thermal protection circuitry disables the outputs if the chip temperature exceeds the safe limits. powerso36 table 1. device summary order code package packing E-L6258EX powerso36 tube E-L6258EXtr powerso36 tape&reel www.st.com
contents l6258ex 2/32 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 input logic (i0 - i1 - i2 - i3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 phase input ( ph ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 triangular generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 current control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 pwm current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 open loop transfer function analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 load attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 error amplifier and sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 effect of the bemf on the current control loop stability . . . . . . . . . . . . . . . 22 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 motor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 unused inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 notes on pcb design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 operation mode time di agrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
l6258ex list of tables 3/32 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. charge pump capacitor's values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of figures l6258ex 4/32 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. power bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. current control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. output comparator waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. ax bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. aloop bode plot (uncompensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. aloop bode plot (compensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. electrical model of the load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. full step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 13. half step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. 4 bit microstep operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. powerso36 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
l6258ex block diagram 5/32 1 block diagram figure 1. block diagram dac charge pump v r (v dd /2) vcp1 ph_1 i0_1 i1_1 i2_1 vref1 triangle generator tri_cap error amp + - v r + - + - c c power bridge 1 tri_0 tri_180 tri_180 tri_0 dac ph_2 i0_2 i1_2 i2_2 vref1 error amp + - v r + - + - c c power bridge 2 tri_0 tri_180 thermal prot. out1a out1b r s sense1a vboot disable vs out2a out2b sense2a r s vs ea_in2 ea_out2 gnd ea_in1 ea_out1 vcp2 v dd (5v) d96in430d vr gen input & sense amp c p c fref c boot input & sense amp i3_1 i3_2 sense1b sense2b r c1 r 1 1m r 2 1m r c2 c c2 c c1 table 2. absolute maximum rating parameter description value unit v s supply voltage 45 v v dd logic supply voltage 7 v v ref1 /v ref2 reference voltage 2.5 v i o output current (peak) (1) 1. this current is intended as not r epetitive current for max. 1 second. 2a i o output current (continuous) 1.5 a v in logic input voltage range -0.3 to 7 v v boot bootstrap supply 60 v v boot - v s maximum vgate applicable 15 v t j junction temperature 150 c t stg storage temperature range -55 to 150 c
block diagram l6258ex 6/32 figure 2. pin connection (top view) table 3. pin functions pin # name description 1, 36 pwr_gnd ground connection (1). they also conduct heat from die to printed circuit copper. 2, 17 ph_1, ph_2 these ttl compatible logic inputs set the direction of current flow through the load. a high level causes current to flow from output a to output b. 3i 1_1 logic input of the internal dac (1). the output voltage of the dac is a percentage of the vref voltage applied according to the thruth table 5 on page 12 . 4i 0_1 see pin 3 5 out1a bridge output connection (1) 6 disable disables the bridges for additional safety during switching. when not connected the bridges are enabled 7tri_cap triangular wave generation circuit capacitor. the value of this capacitor defines the output switching frequency pwr_gnd ph_2 ea_in2 ea_out2 disable ea_out1 out1a ea_in1 ph_1 sense1 out1b i3_1 vs i2_1 i3_2 out2b sense2 pwr_gnd 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 pwr_gnd pwr_gnd d96in432e gnd tri_cap v cc i0_1 vref1 i1_1 9 8 7 28 29 30 vcp1 sig_gnd 10 27 out2a vcp2 vboot vref2 i2_2 i0_2 14 12 11 23 25 26 vs i1_2 13 24
l6258ex block diagram 7/32 note: the number in parenthesis shows the relevant power bridge of the circuit. pins 18, 19, 1 and 36 are connected together. 8v dd (5v) supply voltage input for logic circuitry 9 gnd power ground connection of the internal charge pump circuit 10 v cp1 charge pump oscillator output 11 v cp2 input for external charge pump capacitor 12 v boot overvoltage input for driving of the upper dmos 13, 31 v s supply voltage input for output stage. they are shorted internally 14 out2a bridge output connection (2) 15 i 0_2 logic input of the internal dac (2). the output voltage of the dac is a percentage of the vref voltage applied according to the truth table 5 on page 12 . 16 i 1_2 see pin 15 18, 19 pwr_gnd ground connection. they also conduct heat from die to printed circuit copper 20, 35 sense2, sense1 negative input of the transconductance input amplifier (2, 1) 21 out2b bridge output connection an d positive input of the tranconductance (2) 22 i 3_2 see pin 15 23 i 2_2 see pin 15 24 ea_out_2 error amplifier output (2) 25 ea_in_2 negative input of error amplifier (2) 26, 28 v ref2 , v ref1 reference voltages for the internal dacs, determining the output current value. output current also depends on the logic inputs of the dac and on the sensing resistor value 27 sig_gnd signal ground connection 29 ea_in_1 negative input of error amplifier (1) 30 ea_out_1 error amplifier output (1) 32 i 2_1 see pin 3 33 i 3_1 see pin 3 34 out1b bridge output connection an d positive input of the tranconductance (1) table 3. pin functions (continued) pin # name description
block diagram l6258ex 8/32 figure 3. thermal characteristics table 4. electrical characteristics (v s = 40v; v dd = 5v; t j = 25; unless otherwise specified.) parameter description test condition min. typ. max. unit v s supply voltage 12 40 v v dd logic supply voltage 4.75 5.25 v v boot storage voltage v s = 12 to 40v v s +6 v s +12 v v sense max drop across sense resistor 1.25 v v s(off) power off reset off threshold 6 7.2 v v dd(off) power off reset off threshold 3.3 4.1 v i s(on) v s quiescent current both bridges on, no load 15 ma i s(off) v s quiescent current both bridges off 7 ma i dd v dd operative current 15 ma conditions power dissipated (w) t ambient (?c) thermal j-a resistance (?c/w) 5.3 70 15 4.0 70 20 2.3 70 35 pad layout + ground layers + 16 via hol pcb ref.: 4 layer cm 12 x 12 pad layout + ground layers pcb ref.: 4 layer cm 12 x 12 pad layout + 6cm2 on board heat sink pcb ref.: 2 layer cm 12 x 12 d02in1370 0 0 2 4 6 8 15?c/w 20?c/w 35?c/w 10 12 20 40 60 80 100 120 140 160 ambient temperature (?c) power dissipated (w) d02in1371
l6258ex block diagram 9/32 t sd-h shut down hysteresis 25 c t sd thermal shutdown 150 c f osc triangular oscillator frequency (1) c fref = 1nf 12.5 15 18.5 khz transistors i dss leakage current off state 500 a r ds(on) on resistance on state 0.6 0.75 w v f flywheel diode voltage if =1.0a 1 1.4 v control logic v in(h) lnput voltage all inputs 2 v dd v v in(l) input voltage all inputs 0 0.8 v i in input current (2) 0 < v in < 5v -150 +10 a i dis disable pin input current -10 +150 a v ref1 / ref2 reference voltage operating 0 2.5 v i ref v ref terminal input current v ref = 1.25 -2 5 a fi = v ref /v sense pwm loop transfer ratio 2 v fs dac full scale precision v ref = 2.5v i 0 /i 1 /i 2 /i 3 = l 1.23 1.34 v v offset current loop offset v ref = 2.5v i 0 /i 1 /i 2 /i 3 = h -40 +40 mv dac factor ratio normalized @ full scale value -2 +2 % sense amplifier v cm lnput common mode voltage range -0.7 v s +0.7 v i inp input bias sense1/sense2 -200 0 a error amplifier g v open loop voltage gain 70 db sr output slew rate open loop 0.2 v/ s gbw gain bandwidth product 400 khz 1. chopping frequency is twice fosc value. 2. this is true for all the logi c inputs except the disable input. table 4. electrical characteristics (continued) (v s = 40v; v dd = 5v; t j = 25; unless otherwise specified.) parameter description test condition min. typ. max. unit
functional description l6258ex 10/32 2 functional description the circuit is intended to drive both windings of a bipolar stepper motor or two dc motors. the current control is generated through a switch mode regulation. with this system the direction and the amplitude of the load current are depending on the relation of phase and duty cycle between the two outputs of the current control loop. the l6258ex power stage is composed by power dmos in bridge configuration as it is shown in figure 4 , where the bridge outputs out_a and out_b are driven to v s with an high level at the inputs in_a and in_b while are driven to ground with a low level at the same inputs. the zero current condition is obtained by driving the two half bridge using signals in_a and in_b with the same phase and 50% of duty cycle. in this case the outputs of the two half bridges are continuously switched between power supply (v s ) and ground, but keeping the differential voltage across the load equal to zero. in figure 4 is shown the timing diagram of the two outputs and the load current for this working condition. following we consider positive the current flowing into the load with a direction from out_a to out_b, while we consider negative the current flowing into load with a direction from out_b to out_a. now just increasing the duty cycle of the in _a signal and decreasin g the duty cycle of in_b signal we drive positive current into the load. in this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge formed by t1 and t4 when the output out_a is driven to v s and the output out_b is driven to ground, while there will be a cu rrent recirculation into the higher side of the bridge, through t1 and t2, when both the outputs are at vs and a current recirculation into the lower side of the bridge, through t3 and t4, when both the outputs are connected to ground. since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is higher than the current charging time constant during the period in which the current flows into the load through the diagonal bridge formed by t1 and t4. in this way the load current will be positive with an average amplitude de pending on the difference in duty cycle of the two driving signals. in figure 4 is shown the timing diagram in the case of positive load current on the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the in_a signal and increase the duty cycle of the in_b signal. in this way we obtain a phase shift between the two outputs such to have current flowing into the diagonal bridge formed by t2 and t3 when the output out_a is driven to ground and output out_b is driven to vs, while we will have the same current recirc ulation conditions of the previous case when both the outputs are driven to vs or to ground. so, in this case the load current will be n egative with an average amplitude always depending by the difference in dut y cycle of the two driving signals. in figure 4 is shown the timing diagram in the case of negative load current. figure 5 shows the device block diagram of the complete current control loop.
l6258ex functional description 11/32 2.1 reference voltage the voltage applied to vref pin is the reference for the internal dac and, together with the sense resistor value, defines the maximum current into the motor winding according to the following relation: where r s = sense resistor value figure 4. power bridge configuration i max 0,5 v ref ? r s ----------------------------- - 1 fi ----- v ref r s -------------- ? == load out_a out_b t1 t3 t2 t4 in_a in_b v s 0 outa outb iload 0 outa outb iload 0 outa outb iload fig. 4a fig. 4b fig. 4c d97in624
functional description l6258ex 12/32 figure 5. current control loop block diagram 2.2 input logic (i 0 - i 1 - i 2 - i 3 ) the current level in the motor winding is selected according to this table: dac + - + - vdac ia ic rc cc v r + - ib + - + - error ampl. input transconductance ampl. vs vs r l l l r s load outa outb vref i0 i1 i2 i3 ph gin=1/ra vsense gs=1/rb tri_180 power ampl. sense transconductance ampl. d97in625 tri_0 table 5. current levels i3 i2 i1 i0 current level % of imax hhhh no current hhhl 9.5 hhlh 19.1 hhl l 28.6 hlhh 38.1 hlhl 47.6 hllh 55.6 hlll 63.5 lhhh 71.4 lhhl 77.8 lhlh 82.5
l6258ex functional description 13/32 2.3 phase input ( ph ) the logic level applied to this input determines the direction of the current flowing in the winding of the motor. high level on the phase input causes the motor current flowing from out_a to out_b through the load. 2.4 triangular generator this circuit generates the two triangular waves tri_0 and tri_180 internally used to generate the duty cycle variation of the signals driving the output stage in bridge configuration. the frequency of the triangular wave defines the switching frequency of the output, and can be adjusted by changing the capacitor connected at tr1_cap pin: where: k = 1.5 x 10 -5 2.5 charge pump circuit to ensure the correct driving of the high side drivers a voltage higher than vs is supplied on the vboot pin. this boostrap voltage is not needed for the low side power dmos transistors because their sources terminals are grounded. to produce this voltage a charge pump method is used. it is made by using two external capacitors; one connected to the internal oscillator (cp) and the other (cboot) to stor age the overvolt age needed for t he driving the gates of the high side dmos. the value suggested for the capacitors are: lhll 88.9 llhh 92.1 llhl 95.2 lllh 98.4 llll 100 table 5. current levels (continued) i3 i2 i1 i0 current level % of imax f ref k c --- - = table 6. charge pump capacitor's values component name componen t's function value unit c boot storage capacitor 100 nf c p pump capacitor 10 nf
functional description l6258ex 14/32 2.6 current control loop the current control loop is a transconductance amplifier working in pwm mode. the motor current is a function of the programmed dac voltage. to keep under control the output current, the current control modulates the duty cycle of the two outputs out_a and out_b, and a sensing resistor rs is connected in series with the motor winding in order to produce a voltage feedback compared with the programmed voltage of the dac. the duty cycle modulation of the two outputs is generated comparing the voltage at the outputs of the error amplifier, with the two triangular wave references. in order to drive the output bridge with the duty cycle modulation explained before, the signals driving each output (outa & outb) are generated by the use of the two comparators having as reference two triangular wave signals tri_0 and tri_180 of the same amplitude, the same average value (in our case vr), but with a 180 of phase shift each other. the two triangular wave references are respectively applied to the inverting input of the first comparator and to the non inverting input of the second comparator. the other two inputs of the comparators are connected together to the error amplifier output voltage resulting by the difference between the programmed dac. the reset of the comparison between the mentioned signals is shown in figure 6 . figure 6. output comparator waveforms in the case of v dac equal to zero, the transconductance loop is balanced at the value of vr, so the outputs of the two comparators are signals having the same phase and 50% of duty cycle. as we have already mentioned, in this situation, the two outputs out_a and out_b are simultaneously driven from v s to ground; and the differential voltage across the load in this case is zero and no current flows in the motor winding. tri_0 tri_180 error ampl. output first comp. output second comp. output
l6258ex functional description 15/32 with a positive differential voltage on v dac (see figure 5 , the transconductance loop will be positively unbalanced respected vr. in this case being the error amplifier output voltage greater than vr, the output of the first comparator is a square wave with a duty cycle higher than 50%, while the output of the second comparator is a square wave with a duty cycle lower than 50%. the variation in duty cycle obtained at the outputs of the two comparators is the same, but one is positive and the other is negative with respect to the 50% level. the two driving signals, generated in this case, drive the two outputs in such a way to have switched current flowing from out_a through the motor winding to out_b. with a negative differential voltage v dac , the transconductance loop will be negatively unbalanced respected vr. in this case the output of the first comparator is a square wave with a duty cycle lower than 50%, while the output of the second comparator is a square wave with a duty cycle higher than 50%. the variation in the duty cycle obtained at the outputs of the two comparators is always of the same. the two driving signals, generated in this case, drive the the two outputs in order to have the switched current flowing from out_b through the motor winding to out_a. 2.7 current control loop compensation in order to have a flexible system able to driv e motors with different elec trical characteristics, the non inverting input and the output of the error amplifier ( ea_out ) are available. connecting at these pins an external rc compensation network it is possible to adjust the gain and the bandwidth of the current control loop.
pwm current control loop l6258ex 16/32 3 pwm current control loop 3.1 open loop transfer function analysis block diagram: refer to figure 5. input parameters: v s = 24v l l = 12mh r l = 12 r s = 0.33 r c = to be calculated c c = to be calculated gs transconductance gain = 1/rb gin transconductance gain = 1/ra ampl. of the tria_0_180 ref. = 1.6v (peak to peak) r a = 40k r b = 20k v r = internal reference equal to v dd /2 (typ. 2.5v) these data refer to a typical application, an d will be used as an example during the analysis of the stability of the current control loop. the block diagram shows the schematics of the l6258ex internal current control loop working in pwm mode; the current into the load is a function of the input control voltage v dac , and the relation between the two variables is given by the following formula: i load r s g s = v dac g in where: v dac is the control voltage defining the load current value g in is the gain of the input transconductance amplifier ( 1/ra ) g s is the gain of the sense transconductance amplifier ( 1/rb ) r s is the resistor connected in series to the output to sense the load current in this configuration the input voltage is compared with the feedback voltage coming from the sense resistor, then the difference between this two signals is amplified by the error amplifier in order to have an error signal controlling the duty cycle of the output stage keeping the load current under control. it is clear that to have a good performance of the current control loop, the error amplifier must have an high dc gain and a large bandwidth. i load r s 1 r b ------- ?? v dac 1 r a ------- ? = i load v dac r b r a r s ? ---------------------- ? 0,5 v dac r s -------------- - a () ? ==
l6258ex pwm current control loop 17/32 gain and bandwidth must be chosen depending on many parameters of the application, like the characteristics of the load, power supply etc. .., and most important is the stability of the system that must always be guaranteed. to have a very flexible system and to have the possibility to adapt the system to any application, the error amplifier must be compensated using an rc network connected between the output and the negative input of the same. for the evaluation of the stabilit y of the system, we have to c onsider the open loop gain of the current control loop: aloop = acerr acpw acload acsense where ac... is the gain of the blocks that refers to the error, power and sense amplifier plus the attenuation of the load block. the same formula in db can be written in this way: aloop db = acerr db + acpw db + acload db + acsense db so now we can start to analyse the dynamic characteristics of each single block, with particular attention to the error amplifier. 3.2 power amplifier the power amplifier is not a linear amplifier, but is a circuit driving in pwm mode the output stage in full bridge configuration. the output duty cycle variation is given by the comparison between the voltage of the error amplifier and two triangular wave references tri_0 and tri_180. because all the current control loop is referred to the vr reference, the result is that when the output voltage of the error amplifier is equal to the vr voltage the two output out_a and out_b have the same phase and duty cycle at 50%; increasing the output voltage of the error amplifier above the vr voltage, the duty cycle of the out_a increases and the duty cycle of the out_b decreases of the same percentage; on the contrary decreasing the voltage of the error amplifier below the vr voltage, the duty cycle of the out_a decreases and the duty cycle of the out_b increases of the same percentage. the gain of this block is defined by the amplitude of the two triangular wave references; more precisely the gain of the power amplifier block is a reversed proportion of the amplitude of the two references. in fact a variation of the error amplifier output voltage produces a larger variation in duty cycle of the two outputs out_a and out_b in case of low amplitude of the two triangular wave references. the duty cycle has the max value of 100% when the input voltage is equal to the amplitude of the two triangular references. the transfer function of this block consist in the relation between the output duty cycle and the amplitude of the triangular references. vout = 2 v s (0.5 - dutycycle) acpw db 20 v out v in ---------------- log ? 2v s ? triangular amplitude ------------------------------------------------------ - ==
pwm current control loop l6258ex 18/32 moreover, having the two references tri_0 and tri_180 a triangular shape it is clear that the transfer function of this block is a li near constant gain without poles and zeros. 3.3 load attenuation the load block is composed by the equivalent circuit of the motor winding (resistance and inductance) plus the sense resistor. we will considered the effect of the bemf voltage of the motor in the next chapter. the input of this block is the pwm voltage of the power amplifier and as output we have the voltage across the sense resistor produced by the current flowing into the motor winding. the relation between the two variable is: so the gain of this block is: where: r l = equivalent resistance of the motor winding r s = sense resistor because of the inductance of the motor l l , the load has a pole at the frequency: acpw db 20 224 ? 1,6 ---------------- - log ? 29,5db == v sense v out r l r s + ---------------------- r s ? = acload v sense v out --------------------- r s r l r s + ---------------------- == acload db 20 r s r l r s + ---------------------- log ? = aload db 20 0,33 12 0,33 + ------------------------ log ? 31,4db ? == fpole 1 2 l l r l r s + -------------------- - ? ----------------------------------- = fpole 1 6,28 12 10 3 ? ? 12 0,33 + -------------------------- - ? ---------------------------------------------- 163hz ==
l6258ex pwm current control loop 19/32 before analysing the error amplifier block and the sense transconductance block, we have to do this consideration: aloop db = ax db + bx db ax| db = acpw| db + acload| db and bx| db = acerr| db + acsense| db this means that ax|db is the sum of the power amplifier and load blocks; ax| db = (29,5) + (-31.4) = -1.9db the bode analysis of the transfer function of ax is: figure 7. ax bode plot the bode plot of the ax|db function shows a dc gain of -1.9db and a pole at 163hz. it is clear now that (because of the negative gain of the ax function), bx function must have an high dc gain in order to increment the total open loop gain increasing the bandwidth too. 3.4 error amplifier and sense amplifier as explained before the gain of these two blocks is: bx db = acerr db + acsense db being the voltage across the sense resistor the input of the bx block and the error amplifier voltage the output of the same, the voltage gain is given by: ib vsense gs ? vsense 1 rb ------- - ? ==
pwm current control loop l6258ex 20/32 verr_out = -(ic zc) so ic = -(verr_out ) because ib = icwe have: vsense = -(verr_out ) in the case of no external rc network is used to compensate the error amplifier, the typical open loop transfer function of the error plus the sense amplifier is something with a gain around 80db and a unity gain bandwidth at 400khz. in this case the situation of the total transfer function aloop, given by the sum of the ax db and bx db is: figure 8. aloop bode plot (uncompensated) the bode diagram shows together the error amplifier open loop transfer function, the ax function and the resultant total aloop given by the following equation: aloop db = axdb + bx db the total aloop has an high dc gain of 78.1db with a bandwidth of 15khz, but the problem in this case is the stability of the system; in fact the total aloop cross the zero db axis with a slope of -40db/decade. now it is necessary to compensate the error amplifier in order to obtain a total aloop with an high dc gain and a large bandwidth. aloop must have enough phase margin to guarantee the stability of the system. a method to reach the stability of the system, using the rc network showed in the block diagram, is to cancel the load pole with the zero given by the compensation of the error amplifier. the transfer function of the bx block with the compensation on the error amplifier is: 1 zc ------ - 1 rb ------- - 1 zc ------ - bx verr_out vsense ----------------------- - ? zc rb ------- - ? ==
l6258ex pwm current control loop 21/32 in this case the bx block has a dc gain equal to the open loop and equal to zero at a frequency given by the following formula: in order to cancel the pole of the load, the zero of the bx block must be located at the same frequency of 163hz; so now we have to find a compromise between the resistor and the capacitor of the compensation network. considering that the resistor value defines the gain of the bx block at the zero frequency, it is clear that this parameter will influence th e total bandwidth of the system because, annulling the load pole with the erro r amplifier zero, the slope of the total transfer function is -20db/decade. so the resistor value must be chosen in order to have an error amplifier gain enough to guarantee a desired total bandwidth. in our example we fix at 35db the gain of the bx block at zero frequency, so from the formula: where: rb = 20k we have: rc = 1.1m therefore we have the zero with a 163hz the capacitor value: now we have to analyse how the new aloop transfer function with a compensation network on the error amplifier is. the following bode diagram shows: ? the ax function showing the position of the load pole ? the open loop transfer function of the bx block ? the transfer function of the bx with the rc compensation network on the error amplifier ? the total aloop transfer function that is th e sum of the ax function plus the transfer function of the compensated bx block. bx zc rb ------- - ? rc j 1 2 fcc ?? ------------------------------ ? rb --------------------------------------------- - ? == fzero 1 2 rc cc ?? ------------------------------------ = bx_gain @ zero freq. 20 rc rb ------- - log ? = cc 1 2 fzero rc ? ? --------------------------------------------- 1 6,28 163 1,1 10 6 ? ??? ---------------------------------------------------------------- - 880pf == =
pwm current control loop l6258ex 22/32 figure 9. aloop bode plot (compensated) we can see that the effect of the load pole is cancelled by the zero of the bx block ; the total aloop cross a the 0db axis with a slope of -20d b/decade, having in this way a stable system with an high gain at low frequency and a bandwidth of around 8khz. to increase the bandwidth of the system, we should increase the gain of the bx block, keeping the zero in the same position. in this way the result is a shift of the total aloop transfer function up to a greater value. 3.5 effect of the bemf on the current control loop stability in order to evaluate what is the effect of the bemf voltage of the stepper motor we have to look at the load block:
l6258ex pwm current control loop 23/32 figure 10. electrical model of the load the schematic now shows the equivalent circuit of the stepper motor including a sine wave voltage generator of the bemf. the bemf voltage of the motor is not constant, its value changes depending on the speed of the motor. increasing the motor speed the bemf voltage increases: bemf = kt where: kt is the motor constant is the motor speed in radiant per second the formula defining the gain of the load considering the bemf of the stepper motor becomes: we can see that the bemf influences only the ga in of the load block and does not introduce any other additional pole or zero, so from the stability point of vi ew the effect of the bemf of the motor is not critical because the phase margin remains the same. practically the only effect of the bemf is to limit the gain of the total aloop with a consequent variation of the bandwidth of the system. out+ bemf r l l l out- r s to sense amplifier acload vsense vout --------------------- v s bemf ? () r s r l r s + ---------------------- ? v s ---------------------------------------------------------------- == acload v s bemf ? v s ---------------------------- - r s r l r s + ---------------------- ? = acload db 20 v s bemf ? v s ---------------------------- - r s r l r s + ---------------------- ? ?? ?? ?? log ? =
application information l6258ex 24/32 4 application information a typical application circuit is shown in figure 11 . note: for avoid current spikes on falling edge of disable a "dc feed back" would be added to the error amplifier. (r1-r2 on figure 11 ). 4.1 interference due to the fact that the circuit operates with switch mode current regulation, to reduce the effect of the wiring inductance a good capacitor (100nf) can be placed on the board near the package, between the power supply line (pin 13,31) and the power ground (pin 1,36,18,19) to absorb the small amount of inductive energy. it should be noted that this capacitor is usually required in addition to an electrolytic capacitor, that has poor performance at the high frequencies, always located near the package, between power supply voltage (pin 13,31) and power ground (pin 1,36,18,19), just to have a current recirculation path during the fast current decay or during the phase change. the range value of this capacitor is between few f and 100f, and it must be chosen depending on application parameters like the motor inductance and load current amplitude. a decoupling capacitor of 100nf is suggested also between the logic supply and ground. the ea_in1 and ea_in2 pins carry out high impedance lines and care must be taken to avoid coupled noise on this signals. the suggestion is to put the components connected to this pins close to the l6258ex, to surround them with ground tracks and to keep as far as possible fast switching outputs of the device. remember also an 1 mohm resistor between ea_inx and ea_outx to avoid output current spike during supply startup/shutdown. a non inductive resistor is the best way to implement the sensing. whether this is not possible, some metal film resistor of the same value can be paralleled. the two inputs for the sensing of the winding motor current (sense_a & sense_b) should be connected directly on the sensing resistor rs terminals, and the path lead between the rs and the two sensing inputs should be as short as possible. note: connect the disable pin to a low impedance (< 300 ) voltage source to reduce at minimum the interference on the output current due to capacitive coupling of out1a (pin5) and disable (pin 6).
l6258ex application information 25/32 figure 11. typical application circuit 4.2 motor selection some stepper motor have such high core losses that they are not suitable for switch mode current regulation. furthermore, some stepper motors are not designed for continuous operating at maximum current. since the circuit can drive a constant current through the motor, its temperature might exceed, both at low and high speed operation. 4.3 unused inputs unused inputs should be connected to the proper voltage levels in order to get the highest noise immunity. stepper motor m 12mh 10 0.33 0.33 21 20 14 35 34 5 out2b sense2 out2a sense1 out1b out1a ph1 2 i0_1 4 i1_1 3 i2_1 32 i3_1 33 ph2 17 i0_2 15 i1_2 16 i2_2 23 i3_2 22 disable 6 10nf 100nf 1nf tri_cap 7 vs 13,31 vboot 12 vcp2 11 vcp1 10 9 gnd 1,36 18,19 pwr_gnd vs 27 sig_gnd 28 d97in626ex vref1 26 vref2 29 ea_in1 30 ea_out1 820pf 1m 25 ea_in2 24 ea_out2 820pf 1m vref 8 v dd v dd (5v) l6258ex pwsso36 package r2 1m r1 1m
application information l6258ex 26/32 4.4 notes on pcb design we recommend to observe the following layout rules to avoid application problems with ground and anomalous recirculation current. the by-pass capacitors for the power and logic supply must be kept as near as possible to the ic. it's important to separate on the pcb board the logic and power grounds and the internal charge pump circuit ground avoiding that ground traces of the logic signals cross the ground traces of the power signals. because the ic uses the board as a heat sink, the dissipating copper area must be sized in accordance with the required value of r thj-amb .
l6258ex operation mode time diagrams 27/32 5 operation mode time diagrams figure 12. full step operation mode timing diagram (phase - dac input and motor current) ph2 full step vector 0 23 1 0 3 2 1 0 position dac 2 inputs 0 motor drive current 2 0 motor drive current 1 i3_2 i2_2 i1_2 i3_1 0 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v dac 1 inputs phase 2 phase 1 i0_2 i2_1 i1_1 i0_1 0 3 2 1 ph1 ph2 ph1 d97in629a 95.2% 19.1% 95.2% 19.1% i3 i2 i1 i0 current level% of i max 0000 100 0001 98.4 0010 95.2 0011 92.1 0100 88.9 0101 82.5 0110 77.8 0111 71.4 1000 63.5 1001 55.6 1010 47.6 1011 38.1 1100 28.6 1101 19.1 1110 9.5 1 1 1 1 no current
operation mode time diagrams l6258ex 28/32 figure 13. half step opera tion mode timing diagram (phase - dac input and motor current) ph2 half step vector 67 45 13 2 0 dac 2 inputs motor drive current 2 71.4% 100% 0 motor drive current 1 i3_2 i2_2 i1_2 i3_1 0 71.4% 100% -71.4% -100% -71.4% -100% 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v dac 1 inputs phase 2 phase 1 i0_2 i2_1 i1_1 i0_1 2 1 0 7 6 5 4 3 ph1 ph2 ph1 d97in627c i3 i2 i1 i0 current level% of i max 0000 100 0001 98.4 0010 95.2 0011 92.1 0100 88.9 0101 82.5 0110 77.8 0111 71.4 1000 63.5 1001 55.6 1010 47.6 1011 38.1 1100 28.6 1101 19.1 1110 9.5 1111 no current
l6258ex operation mode time diagrams 29/32 figure 14. 4 bit microstep operation mode timing diagram (phase - dac input and motor current) ph2 micro step vector 32 24 28 20 16 12 8 4 0 position dac 2 inputs 0 motor drive current 2 0 motor drive current 1 i3_2 i2_2 i1_2 i3_1 0 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v 0 5v dac 1 inputs phase 2 phase 1 i0_2 i2_1 i1_1 i0_1 16 8 0 56 48 40 32 24 ph1 ph2 ph1 d97in628a 60 64 56 52 48 44 40 36 100% 95.2% 82.5% 63.5% 47.6% 38.1% 0% 19.1% i3 i2 i1 i0 current level% of i max 0000 100 0001 98.4 0010 95.2 0011 92.1 0100 88.9 0101 82.5 0110 77.8 0111 71.4 1000 63.5 1001 55.6 1010 47.6 1011 38.1 1100 28.6 1101 19.1 1110 9.5 1111 no current
package information l6258ex 30/32 6 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 15. powerso36 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0.0039 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 d 15.80 16.00 0.6220 0.6299 d1 9.40 9.80 0.3701 0.3858 e 13.90 14.5 0.5472 0.5709 e1 10.90 11.10 0.4291 0.4370 e2 2.90 0.1142 e3 5.80 6.20 0.2283 0.2441 e 0.65 0.0256 e3 11.05 0.4350 g 0 0.10 0.0039 h 15.50 15.90 0.6102 0.6260 h 1.10 0.0433 l 0.8 1.10 0.0315 0.0433 n 10? (max) s 8? (max) note: ?d and e1? do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006?) - critical dimensions are "a3", "e" and "g". powerso-36 0096119 c
l6258ex revision history 31/32 7 revision history table 7. document revision history date revision changes 15-sep-2003 1 first issue in the edocs dms. 11-may-2004 2 restyling of the graphic form, changed all v cc with v dd ; delete tsd parameter in the electrical characteristic on ta b l e 4 . 24-sep-2004 3 changed on the page 5 the f osc parameter max. value from 17.5 to 18.5khz 28-feb-2005 4 add. note at the bottom of table 2: absolute maximum rating . 23-mar-2005 5 modified the note ?(1)? of the ta bl e 2 . 03-dec-2007 6 document reformatted. modified the acpw formula in section 3.2 on page 17 . added the disable note in section 4.1 on page 24 .
l6258ex 32/32 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st? terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user? own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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